43d241c28d
- Add arena allocator for zero-allocation hot paths - Add thread pool for parallel operations - Add mmap utilities for memory-mapped I/O - Implement queue_index with heap-based priority queue - Implement dataset_hash with SIMD support (SHA-NI, ARMv8) - Add runtime SIMD detection for cross-platform correctness - Add comprehensive tests and benchmarks
103 lines
3.5 KiB
C++
103 lines
3.5 KiB
C++
#include "sha256_base.h"
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// ARMv8-A Cryptographic Extensions implementation
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#if defined(__aarch64__) || defined(_M_ARM64)
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#include <arm_neon.h>
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static void transform_armv8(uint32_t* state, const uint8_t* data) {
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// Load the 512-bit message block into 4 128-bit vectors
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uint32x4_t w0 = vld1q_u32((const uint32_t*)data);
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uint32x4_t w1 = vld1q_u32((const uint32_t*)(data + 16));
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uint32x4_t w2 = vld1q_u32((const uint32_t*)(data + 32));
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uint32x4_t w3 = vld1q_u32((const uint32_t*)(data + 48));
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// Reverse byte order (SHA256 uses big-endian words)
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w0 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(w0)));
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w1 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(w1)));
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w2 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(w2)));
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w3 = vreinterpretq_u32_u8(vrev32q_u8(vreinterpretq_u8_u32(w3)));
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// Load current hash state
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uint32x4_t abcd = vld1q_u32(state);
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uint32x4_t efgh = vld1q_u32(state + 4);
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uint32x4_t abcd_orig = abcd;
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uint32x4_t efgh_orig = efgh;
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// Rounds 0-15 with pre-expanded message
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uint32x4_t k0 = vld1q_u32(&K[0]);
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uint32x4_t k1 = vld1q_u32(&K[4]);
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uint32x4_t k2 = vld1q_u32(&K[8]);
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uint32x4_t k3 = vld1q_u32(&K[12]);
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uint32x4_t tmp = vaddq_u32(w0, k0);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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tmp = vaddq_u32(w1, k1);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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tmp = vaddq_u32(w2, k2);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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tmp = vaddq_u32(w3, k3);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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// Rounds 16-63: Message schedule expansion + rounds
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for (int i = 16; i < 64; i += 16) {
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// Schedule expansion for rounds i..i+3
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uint32x4_t w4 = vsha256su0q_u32(w0, w1);
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w4 = vsha256su1q_u32(w4, w2, w3);
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k0 = vld1q_u32(&K[i]);
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tmp = vaddq_u32(w4, k0);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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// Schedule expansion for rounds i+4..i+7
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uint32x4_t w5 = vsha256su0q_u32(w1, w2);
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w5 = vsha256su1q_u32(w5, w3, w4);
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k1 = vld1q_u32(&K[i + 4]);
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tmp = vaddq_u32(w5, k1);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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// Schedule expansion for rounds i+8..i+11
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uint32x4_t w6 = vsha256su0q_u32(w2, w3);
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w6 = vsha256su1q_u32(w6, w4, w5);
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k2 = vld1q_u32(&K[i + 8]);
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tmp = vaddq_u32(w6, k2);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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// Schedule expansion for rounds i+12..i+15
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uint32x4_t w7 = vsha256su0q_u32(w3, w4);
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w7 = vsha256su1q_u32(w7, w5, w6);
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k3 = vld1q_u32(&K[i + 12]);
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tmp = vaddq_u32(w7, k3);
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efgh = vsha256h2q_u32(efgh, abcd, tmp);
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abcd = vsha256hq_u32(abcd, efgh, tmp);
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// Rotate working variables
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w0 = w4; w1 = w5; w2 = w6; w3 = w7;
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}
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// Add original state back
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abcd = vaddq_u32(abcd, abcd_orig);
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efgh = vaddq_u32(efgh, efgh_orig);
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// Store result
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vst1q_u32(state, abcd);
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vst1q_u32(state + 4, efgh);
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}
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TransformFunc detect_armv8_transform(void) {
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return transform_armv8;
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}
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#else // No ARMv8 support
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TransformFunc detect_armv8_transform(void) { return nullptr; }
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#endif
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